may 1996 NDS9435A single p-channel enhancement mode field effect transistor general description features ____________________________________________________________________________________________ absolute maximum ratings t a = 25c unless otherwise noted symbol parameter NDS9435A units v dss drain-source voltage -30 v v gss gate-source voltage 20 v i d drain current - continuous (note 1a) 5.3 a - pulsed 20 p d maximum power dissipation (note 1a) 2.5 w (note 1b) 1.2 (note 1c) 1 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 50 c/w r q jc thermal resistance, junction-to-case (note 1) 25 c/w NDS9435A rev b these p-channel enhancement mode power field effect transistors are produced using fairchild's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. these devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. -5.3 a, -30v. r ds(on ) = 0.05 w @ v gs = -10v r ds(on ) = 0.07 w @ v gs = -6v r ds(on ) = 0.09 w @ v gs = -4.5v . high density cell design for extremely low r ds(on). high power and current handling capability in a widely used surface mount package. s d s s so-8 d d d g pin 1 ? 1999 fairchild semiconductor corporation 5 6 8 3 1 7 4 2
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = -250 a -30 v i dss zero gate voltage drain current v ds = -24 v, v gs = 0 v -1 a v ds = -15 v, v gs = 0 v t j = 70 c -5 a i gssf gate - body leakage, forward v gs = 20 v, v ds = 0 v 100 na i gssr gate - body leakage, reverse v gs = -20 v, v ds = 0 v -100 na on characteristics (note 2) v gs (th) gate threshold voltage v ds = v gs , i d = -250 a -1 -1.4 v t j = 125 c -0.7 -1 r ds(on) static drain-source on-resistance v gs = -10 v, i d = -5.3 a 0.038 0.05 w t j = 125 c 0.054 0.1 v gs = -6 v, i d = -4.7 a 0.046 0.07 v gs = -4.5 v, i d = -4.2 a 0.064 0.09 i d (on) on-state drain current v gs = -10 v, v ds = -5 v -20 a v gs = -4.5, v ds = -5v -5 g fs forward transconductance v ds = 15 v, i d = 5.3 a 10 s dynamic characteristics c iss input capacitance v ds = 15 v, v gs = 0 v, f = 1.0 mhz 950 pf c oss output capacitance 610 pf c rss reverse transfer capacitance 220 pf switching ch aracteristics (note 2 ) t d(on ) turn - on delay time v dd = -15 v, i d = -1 a, v gen = -10 v, r gen = 6 w 10 30 ns t r turn - on rise time 18 60 ns t d(off) turn - off delay time 80 120 ns t f turn - off fall time 45 100 ns q g total gate charge v ds = -15 v, i d = -5.3 a, v gs = -10 v 29 40 nc q gs gate-source charge 3 nc q gd gate-drain charge 9 nc NDS9435A rev b
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions min typ max units drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current -1.9 a v sd drain-source diode forward voltage v gs = 0 v, i s = -5.3 a (note 2 ) 0.85 -1.3 v t rr reverse recovery time v gs = 0v, i f = -5.3 a, di f /dt = 100 a/s 100 ns notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the so lder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. p d ( t ) = t j - t a r q j a ( t ) = t j - t a r q j c + r q c a ( t ) = i d 2 ( t ) r d s ( o n ) @ t j typical r q ja using the board layouts shown below on 4.5"x5" fr-4 pcb in a still air environment : a. 50 o c/w when mounted on a 1 in 2 pad of 2oz cpper. b. 105 o c/w when mounted on a 0.04 in 2 pad of 2oz cpper. c. 125 o c/w when mounted on a 0.006 in 2 pad of 2oz cpper. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. NDS9435A rev b 1a 1b 1c
NDS9435A rev b -5 -4 -3 -2 -1 0 -30 -25 -20 -15 -10 -5 0 v , drain-source voltage (v) i , drain-source current (a) -6.0 -4.0 v =-10v gs ds d -3.0 -4.5 -3.5 -5.0 -20 -16 -12 -8 -4 0 0.5 1 1.5 2 2.5 3 i , drain current (a) drain-source on-resistance v = -3.5v gs d r , normalized ds(on) -6.0v -10v -6.0v -5.0v -4.0v -4.5v figure 1. on-region characteristics figure 2. on-resistance variation with drain current and gate voltage typical electrical characteristics -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j v = -10v gs i = -5.3a d r , n o r m a l i z e d d s ( o n ) -20 -15 -10 -5 0 0.5 1 1.5 2 i , drain current (a) drain-source on-resistance d r , normalized ds(on) 25c -55c v = -10v gs t = 125c j figure 3. on-resistance variation with temperature figure 4. on-resistance variation with drain current and temperature -5 -4 -3 -2 -1 -20 -16 -12 -8 -4 0 -v , gate to source voltage (v) -i , drain current (a) 25 125 v = -10v ds gs d t = -55c j -50 -25 0 25 50 75 100 125 150 0.6 0.7 0.8 0.9 1 1.1 1.2 t , junction temperature (c) gate-source threshold voltage i = -250a d v = v ds gs j v , normalized th figure 5. transfer characteristics figure 6. gate threshold variation with temperature
NDS9435A rev b -50 -25 0 25 50 75 100 125 150 0.94 0.96 0.98 1 1.02 1.04 1.06 1.08 1.1 t , junction temperature (c) drain-source breakdown voltage i = -250a d bv , normalized dss j 0 0.3 0.6 0.9 1.2 1.5 0.001 0.01 0.1 1 5 10 20 -v , body diode forward voltage (v) -i , reverse drain current (a) t = 125c j 25c -55c v = 0v gs sd s figure 7. breakdown voltage variation with temperature figure 8. body diode forward voltage variation with source current and temperature typical electrical characteristics (continued) 0 10 20 30 40 0 2 4 6 8 10 q , gate charge (nc) -v , gate-source voltage (v) g gs i = -5.3a d v = -10v ds -15v -20v 0.1 0.3 1 3 10 30 100 200 300 500 1000 2000 3000 -v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss d s -v dd r l v out v gs dut v in r gen g 10% 50% 90% 10% 90% 90% 50% v in v out on off d(off) f r d(on) t t t t t t inverted 10% pulse width figure 9. capacitance characteristics figure 10. gate charge characteristics figure 11. switching test circuit figure 12. switching waveforms
NDS9435A rev b -20 -15 -10 -5 0 0 4 8 12 16 20 i , drain current (a) g , t r a n s c o n d u c t a n c e ( s i e m e n s ) t = -55c j 25c d fs v = -15v ds 125c figure 13. transconductance variation with drain current and temperature figure 16. maximum safe operating area typical electrical and thermal characteristics (continued) 0 0.2 0.4 0.6 0.8 1 2 3 4 5 6 2oz copper mounting pad area (in ) i , steady-state drain current (a) d 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air v = -10v a o gs 0 0.2 0.4 0.6 0.8 1 0.5 1 1.5 2 2.5 2oz copper mounting pad area (in ) steady-state power dissipation (w) 2 1c 1b 1a 4.5"x5" fr-4 board t = 25 c still air a o 0.1 0.2 0.5 1 2 5 10 30 50 0.01 0.03 0.1 0.3 1 3 10 30 - v , drain-source voltage (v) -i , drain current (a) ds d 1s 100ms 10s dc 10ms rds(on) limit 1ms v = -10v single pulse r = see note 1c t = 25c gs a q ja 100us figure 14. so-8 maximum steady-state power dissipation versus copper mounting pad area. figure 15 . maximum steady-state drain current versus copper mounting pad area. figure 17 . transient thermal response curve . note: thermal characterization performed using the conditions described in note 1c. transient thermal response will change depending on the circuit board design. 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t / t 1 2 r (t) = r(t) * r r = see note 1c q ja q ja q ja t - t = p * r (t) q ja a j p(pk) t 1 t 2
soic(8lds) packaging configuration: figure 1.0 components leader tape 1680mm minimum or 210 empty pockets trailer tape 640mm minimum or 80 empty pockets soic(8lds) tape leader and trailer configuration: figure 2.0 cover tape carrier tape note/comments packaging option soic (8lds) packaging information standard (no flow code) l86z f011 packaging type reel size tnr 13" dia rail/tube - tnr 13" dia qty per reel/tube/bag 2,500 95 4,000 box dimension (mm) 343x64x343 530x130x83 343x64x343 max qty per box 5,000 30,000 8,000 d84z tnr 7" dia 500 184x187x47 1,000 weight per unit (gm) 0.0774 0.0774 0.0774 0.0774 weight per reel (kg) 0.6060 - 0.9696 0.1182 f63tn label esd label 343mm x 342mm x 64mm standard intermediate box esd label f63tnr label sample f63tnlabel lot: cbvk741b019 fsid: fds9953a d/c1: d9842 qty1: spec rev: spec: qty: 2500 d/c2: qty2: cpn: n/f: f (f63tnr)3 f 852 nds 9959 soic-8 unit orientation f 852 nds 9959 pin 1 static dissipative embossed carrier tape f63tnr label antistatic cover tape esd label electrostatic sensitive devices do no t shi p or sto re n ear stro ng electrostatic electro magn eti c, mag netic o r r adio active fi eld s tnr date pt numb er peel stren gth min ___ __ ____ __ ___g ms max _____________ gms customized label packaging description: soic-8 parts are shipped in tape. the carrier tape is made from a dissipative (carbon filled) polycarbonate resin. the cover tape is a multilayer film (heat activated adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. these reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. the reels are dark blue in color and is made of polystyrene plastic (anti- static coated). other option comes in 500 units per 7" or 177cm diameter reel. this and some other options are further described in the packaging information table. these full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. one box contains two reels maximum. and these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped. f 852 nds 9959 f 852 nds 9959 f 852 nds 9959 so-8 tape and reel data and package dimensions july 1999, rev. b
? 1998 fairchild semiconductor corporation dimensions are in millimeter pkg type a0 b0 w d0 d1 e1 e2 f p1 p0 k0 t wc tc soic (8lds) (12mm) 6.50 +/-0.10 5.30 +/-0.10 12.0 +/-0.3 1.55 +/-0.05 1.60 +/-0.10 1.75 +/-0.10 10.25 min 5.50 +/-0.05 8.0 +/-0.1 4.0 +/-0.1 2.1 +/-0.10 0.450 +/- 0.150 9.2 +/-0.3 0.06 +/-0.02 p1 a0 d1 p0 f w e1 d0 e2 b0 tc wc k0 t dimensions are in inches and millimeters tape size reel option dim a dim b dim c dim d dim n dim w1 dim w2 dim w3 (lsl-usl) 12mm 7" dia 7.00 177.8 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 2.165 55 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 e 0.606 11.9 e 15.4 12mm 13" dia 13.00 330 0.059 1.5 512 +0.020/-0.008 13 +0.5/-0.2 0.795 20.2 7.00 178 0.488 +0.078/-0.000 12.4 +2/0 0.724 18.4 0.469 e 0.606 11.9 e 15.4 see detail aa dim a max 13" diameter option 7" diameter option dim a max see detail aa w3 w2 max measured at hub w1 measured at hub dim n dim d min dim c b min detail aa notes: a0, b0, and k0 dimensions are determined with respect to the eia/jedec rs-481 rotational and lateral movement requirements (see sketches a, b, and c). 20 deg maximum component rotation 0.5mm maximum 0.5mm maximum sketch c (top view) component lateral movement typical component cavity center line 20 deg maximum typical component center line b0 a0 sketch b (top view) component rotation sketch a (side or front sectional view) component rotation user direction of feed soic(8lds) embossed carrier tape configuration: figure 3.0 soic(8lds) reel configuration: figure 4.0 so-8 tape and reel data and package dimensions, continued july 1999, rev. b
soic-8 (fs pkg code s1) 1 : 1 scale 1:1 on letter size paper di me n si o n s s h ow n be l ow a re in : inches [millimeters] part weight per unit (gram): 0.0774 so-8 tape and reel data and package dimensions, continued september 1998, rev. a 9
trademarks acex? coolfet? crossvolt? e 2 cmos tm fact? fact quiet series? fast ? fastr? gto? hisec? the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function or design. fairchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. tinylogic? uhc? vcx? isoplanar? microwire? pop? powertrench? qfet? qs? quiet series? supersot?-3 supersot?-6 supersot?-8
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